This course covers performance engineering approaches on the CPU core level. This course conveys the required knowledge to develop a thorough understanding of the interactions between software and hardware on the level of a single CPU and the lowest memory hierarchy, i.e., the level-1 cache. Relevant properties of instruction execution on superscalar out-of-order CPUs are explained in detail, and the role of critical path, loop-carried dependencies, and instruction throughput limits is discussed.

Overview

This course covers general computer architecture for x86 and ARM processors, an introduction to (AT&T and AArch64) assembly code, and performance analysis and engineering using the Open Source Architecture Code Analyzer (OSACA) in combination with the Compiler Explorer. Attendees will work with these tools to analyze compiler-generated assembly kernels and assess their performance properties in detail.

Prerequisites

In order to do the hands-on exercises, an up-to-date web browser (e.g., Chrome or Firefox) is required.
Attendees should have a basic understanding of how CPUs work (registers, instruction execution, data transfers) and what “machine instructions” are.
It is recommended for attendees to have a basic understanding of the Roofline model. You can find some information here (lecture slides) and here (publication by S. Williams).
It is recommended (but not strictly necessary) for attendees to have some experience in using the Compiler Explorer. You can watch a two-part intro by Matt Godbolt: part 1 part 2

Core-Level Performance Engineering (online)